8051 mcu, von Neumann vs Harvard Architectures

We can classify computer architectures into two categories:

von Neumann architecture: computers has a single, common memory space in which both program instructions and data are stored. There is a single internal data bus that fetches both instructions and data. They can not be performed at the same time.

Harvard architecture: computers have separate memory areas for program instructions and data. There are two or more internal data buses, which allow simultaneous access to both instructions and data. The CPU fetches program instructions on the program memory bus.

The 8051 microcontrollers (MCS-51) have an 8-bit data bus. They can address 64K of external data memory and 64K of external program memory. These may be separate blocks of memory, so that up to 128K of memory can be attached to the microcontroller. Separate blocks of code and data memory are referred to as the Harvard architecture. A single block of memory may be mapped to act as both data and program memory. This is referred to as the Von Neumann architecture.

The 8051 has two separate read signals, RD# (P3.7) and PSEN#. The RD# (P3.7) is activated by clearing to logic level 0 when a byte is to be read from external data memory, PSEN#, from external program memory. All external code is fetched from external program memory. The bytes from external program memory may be read by special read instructions such as the MOVC. And there are separate instructions to read from external data memory, such as the MOVX instruction. In order to read from the same block using either the RD# signal or the PSEN# signal, the two signals are combined with a logic AND operation. This way, the output of the AND gate is low when either input is low.

By adopting the Von Neumann architecture, code may be written to memory as data bytes, and then executed as program instructions.

Further Reading

• 8051 von Neumann Memory Example Program (Keil)


• Harvard vs von Neumann (MSP430 Discussion)

Understanding Processor Architecture: RISC versus CISC

Popular processor designs can be broadly divided into two categories: Complex Instruction Set Computers (CISC) and Reduced Instruction Set Computers (RISC). The dominant processor in the PC market, Pentium, belongs to the CISC category. However, the recent trend is to use the RISC designs. Even Intel has moved from CISC to RISC design for their 64-bit processor.

CISC systems use complex instructions. For example, adding two integers is considered a simple instruction. But, an instruction that copies an element from one array to another and automatically updates both array subscripts is considered a complex instruction. RISC systems use only simple instructions. Furthermore, RISC systems assume that the required operands are in the processor’s internal registers, not in the main memory. It turns out that characteristics like simple instructions and restrictions like register-based operands not only simplify the processor design but also result in a processor that provides improved application performance.

Several factors contributed to the popularity of CISC in the 1970s. In those days, memory was very expensive and small in capacity. Even in the mid-1970s, the price of a small 16 KB memory was about $500. So there was a need to minimize the amount of memory required to store a program. An implication of this requirement is that each processor instruction must do more, leading to complex instruction set designs. Complex instructions meant complex hardware, which was also expensive. This was a problem processor designers grappled with until Wilkes proposed microprogrammed control in the early 1950s.

Figure 1. The ISA-level architecture can be implemented either directly in hardware or through a microprogrammed control.

A microprogram is a small run-time interpreter that takes the complex instruction and generates a sequence of simple instructions that can be executed by the hardware. Thus the hardware need not be complex. Once it became possible to design such complex processors by using microprogrammed control, designers went crazy and tried to close the semantic gap between the instructions of the processor and high-level languages. This semantic gap refers to the fact that each instruction in a high-level language specifies a lot more work than an instruction in the machine language. Think of a while loop statement in a high-level language such as C, for example. If we have a processor instruction with the while loop semantics, we could just use one machine language instruction. This explains why most CISC designs use microprogrammed control, as shown in Figure 1.

RISC designs, on the other hand, eliminate the microprogram layer and use the hardware to directly execute instructions. Here is another reason why RISC processors can potentially give improved performance. One advantage of using microprogrammed control is that we can implement variations on the basic ISA architecture by simply modifying the microprogram; there is no need to change the underlying hardware. Thus it is possible to come up with cheaper versions as well as high-performance processors for the same family of processors.

References

• Guide to RISC Processors for Programmers and Engineers by Sivarama P. Dandamudi, Springer (2005), ISBN 0-387-21017-2.

Learning Machine Code with 8-bit Microcontrollers

To understand deeply in processor architecture, we have to learn the Machine Code. I decide to select the 8051 microcontroller as a microprocessor model. A microcontroller (or MCU) is a computer-on-a-chip. They integrate many modules on one chip such as RAM, Flash memory, EEPROM, serial ports (UARTs), I²C, Serial Peripheral Interface (SPI), analog-to-digital converters (ADC), clock generator (XTAL) and more.

Humans almost never write programs directly in machine code. Instead, they use a programming language which is translated by the computer into machine code. The simplest kind of programming language is assembly language which usually has a one-to-one correspondence with the resulting machine code instructions but allows the use of mnemonics (ASCII strings) for the "op codes" (the part of the instruction which encodes the basic type of operation to perform) and names for locations in the program (branch labels) and for variables and constants.

Installing ASEM-51

ASEM-51 is a two-pass macro assembler for the Intel MCS-51 family of microcontrollers. It is running on the PC under MS-DOS, Windows and Linux. The ASEM-51 assembly language is based on the standard Intel syntax, and implements conditional assembly, macros, and include file processing. The assembler can output object code in Intel-HEX or Intel OMF-51 format as well as a detailed list file. The ASEM-51 package includes support for more than 180 8051 derivatives, a bootstrap program for MCS-51 target boards, and documentation in ASCII and HTML format. And it is free ...

The simplest way of installing ASEM-51 is copying all files of the package to your working directory, and enjoy the benefits of true plug-and-play compatibility!. Alternatively, I have set it up on Windows XP manually:

• Downloads the lastest ASEM-51 for DOS/Windows (currently v1.3)


• Create a new, empty directory on your harddisk (C:\ASEM51).


• Unpack your ASEM-51 distribution archive into this directory, or copy all files of the ASEM-51 package into it.


• Make the scratch directory default, run the batch file INSTALL.BAT provided, and follow the instructions.


• Reboot your PC.

You can update MPU file by downloading http://plit.de/asem-51/mcufiles.zip.

References

• Wikipedia


• machine code from FOLDOC


• Installing MIDE-51 and SDCC and for Win32

Understanding Processor Architecture: Simplify Computer Complexity

Computers are complex systems. We study computer systems by using layers of abstraction. We use a hierarchical structure to simplify the management. Each level of management filters out unnecessary details on the lower levels and presents only an abstracted version to the higher-level management.

People can look at computer systems from several different perspectives depending on the type of their interaction. We use the concept of abstraction to look at only the details that are necessary from a particular viewpoint. For example, a computer user interacts with the system through an application program. Suppose you are interested in browsing the Internet. Your obvious choice is to interact with the system through a Web browser such as the Fire fox (FF) or Internet Explorer (IE). On the other hand, if you are a computer architect, you are interested in the internal details that do not interest a normal user of the system.

From the programmer’s viewpoint, there exists a hierarchy from low-level languages to high-level languages (see Figure 1). At the lowest level, we have the machine language that is the language understood by the machine hardware. Because digital computers use 0 and 1 as their alphabet, machine language naturally uses 1s and 0s to encode the instructions. One level up, there is the assembly language as shown in Figure 1. Assembly language does not use 1s and 0s; instead, it uses mnemonics to express the instructions. Assembly language is closely related to the machine language.

Figure 1. Abstract layers of Computer Systems

References

• Guide to RISC Processors for Programmers and Engineers by Sivarama P. Dandamudi, Springer (2005), ISBN 0-387-21017-2.

Understanding Processor Architecture: ISA

A programmer uses the Instruction Set Architecture (ISA) as an abstraction to understand the processor’s internal details. This abstraction suits us very well as we are interested in the logical details of the processor without getting bogged down by the myriad implementation details.

The ISA specifies how a processor functions: what instructions it executes and what interpretation is given to these instructions. If these specifications are precise, they give freedom to various chip manufacturers to implement physical designs that look functionally the same at the ISA level. Thus, if we run the same program on these different implementations, we still get the same results. For example, the Intel 32-bit ISA (IA-32) has several implementations including the Pentium processors, cheaper Celeron processors, high-performance Xeon processors, and so on.

The ISA-level abstraction provides a common platform to execute programs. If a program is written in C, a compiler translates it into the equivalent machine language program that can run on the ISA-level logical processor. Similarly, if you write your program in FORTRAN, use a FORTRAN compiler to generate code that can execute on the ISA-level logical processor.

References

• Guide to RISC Processors for Programmers and Engineers by Sivarama P. Dandamudi, Springer (2005), ISBN 0-387-21017-2.

P89LPC9381; 8-bit microcontroller with accelerated two-clock 80C51 core 4 kB 3 V byte-erasable flash with 10-bit ADC

The P89LPC9381 is a single-chip microcontroller, available in low-cost packages, based on a high performance processor architecture that executes instructions in two to four clocks, six times the rate of standard 80C51 devices. Many system-level functions have been incorporated into the P89LPC9381 in order to reduce component count, board space, and system cost.

Principal features


• 4 kB byte-erasable flash code memory organized into 1 kB sectors and 64 B pages. Single-byte erasing allows any byte(s) to be used as non-volatile data storage.


• 256 B RAM data memory on-chip RAM.


• 8-input multiplexed 10-bit ADC. Two analog comparators with selectable inputs and reference source.


• Two 16-bit counter/timers (each may be configured to toggle a port output upon timer overflow or to become a PWM output) and a 23-bit system timer that can also be used as a RTC.


• Enhanced UART with fractional baud rate generator, break detect, framing error detection, and automatic address detection; 400 kHz byte-wide I2C-bus communication port and SPI communication port.


• High-accuracy internal RC oscillator option allows operation without external oscillator components. The RC oscillator option is selectable and fine tunable.


• 2.4 V to 3.6 V VDD operating range. I/O pins are 5 V tolerant (may be pulled up or driven to 5.5 V).


• 28-pin TSSOP package with 23 I/O pins minimum and up to 26 I/O pins while using on-chip oscillator and reset options.


Additional features


• A high performance 80C51 CPU provides instruction cycle times of 111 ns to 222 ns for all instructions except multiply and divide when executing at 18 MHz. This is six times the performance of the standard 80C51 running at the same clock frequency. A lower clock frequency for the same performance results in power savings and reduced EMI.


• Serial flash ICP allows simple production coding with commercial EPROM programmers. Flash security bits prevent reading of sensitive application programs.


• Serial flash ISP allows coding while the device is mounted in the end application.


• In-Application Programming of the flash code memory. This allows changing the code in a running application.


• Watchdog timer with separate on-chip oscillator, requiring no external components. The watchdog prescaler is selectable from eight values.


• Low voltage reset (brownout detect) allows a graceful system shutdown when power fails. May optionally be configured as an interrupt.


• Idle and two different power-down reduced power modes. Improved wake-up from Power-down mode (a LOW interrupt input starts execution). Typical power-down current is 1 uA (total power-down with voltage comparators disabled).


• Active-LOW reset. On-chip power-on reset allows operation without external reset components. A reset counter and reset glitch suppression circuitry prevent spurious and incomplete resets. A software reset function is also available.


• Configurable on-chip oscillator with frequency range options selected by user programmed flash configuration bits. Oscillator options support frequencies from 20 kHz to the maximum operating frequency of 18 MHz.


• Oscillator fail detect. The watchdog timer has a separate fully on-chip oscillator allowing it to perform an oscillator fail detect function.


• Programmable port output configuration options: quasi-bidirectional, open-drain, push-pull, input-only.


• Port 'input pattern match' detect. Port 0 may generate an interrupt when the value of the pins match or do not match a programmable pattern.


• LED drive capability (20 mA) on all port pins. A maximum limit is specified for the entire chip.


• Controlled slew rate port outputs to reduce EMI. Outputs have approximately 10 ns minimum ramp times.


• Only power and ground connections are required to operate the P89LPC9381 when internal reset option is selected.


• Four interrupt priority levels.


• Eight keypad interrupt inputs, plus two additional external interrupt inputs.


• Schmitt trigger port inputs.


• Second data pointer.


• Emulation support.

Philips P89V51RD2 Microcontroller

I am using Philips P89V51RD2 as 8051 Microcontroller Unit (MCU). And I have been developing my code with Opensouce C Compiler SDCC. Please visit my Tools page for software preparation guides.

The P89V51RD2 is a 80C51 microcontroller with 64 kB Flash and 1024 bytes of data RAM. A key feature of the P89V51RD2 is its X2 mode option. The design engineer can choose to run the application with the conventional 80C51 clock rate (12 clocks per machine cycle) or select the X2 mode (6 clocks per machine cycle) to achieve twice the throughput at the same clock frequency. Another way to benefit from this feature is to keep the same performance by reducing the clock frequency by half, thus dramatically reducing the EMI.

The Flash program memory supports both parallel programming and in serial In-System Programming (ISP). Parallel programming mode offers gang-programming at high speed, reducing programming costs and time to market. ISP allows a device to be reprogrammed in the end product under software control. The capability to field/update the application firmware makes a wide range of applications possible.

The P89V51RD2 is also In-Application Programmable (IAP), allowing the Flash program memory to be reconfigured even while the application is running.

Features

• 80C51 Central Processing Unit


• 5 V Operating voltage from 0 MHz to 40 MHz


• 64 kB of on-chip Flash user code memory with ISP (In-System Programming) and IAP (In-Application Programming)


• Supports 12-clock (default) or 6-clock mode selection via software or ISP


• SPI (Serial Peripheral Interface) and enhanced UART


• PCA (Programmable Counter Array) with PWM and Capture/Compare functions


• Four 8-bit I/O ports with three high-current Port 1 pins (16 mA each)


• Three 16-bit timers/counters


• Programmable watchdog timer


• Eight interrupt sources with four priority levels


• Second DPTR register


• Low EMI mode (ALE inhibit)


• TTL- and CMOS-compatible logic levels


• Brown-out detection


• Low power modes
  
  o Power-down mode with external interrupt wake-up
  
  o Idle mode


• DIP40 packages

Related Links
Product Page: http://www.semiconductors.philips.com/
Data Sheet: P89V51RB2_RC2_RD2-03.pdf
Boot Loader: p89v_lv51rd2_bl_upd_v5.zip
FlashMagic ISP Software: http://www.esacademy.com/

Introduction to 8051 Microcontroller

The 8051 is an 8 bit microcontroller originally developed by Intel in
1980. It is the world's most popular microcontroller core, made by
many independent manufacturers (truly multi-sourced). There were 126
million 8051s (and variants) shipped in 1993!!

A typical 8051 contains:

• CPU with boolean processor


• 5 or 6 interrupts:
  2 are external
  
  2 priority levels


• 2 or 3 16-bit timer/counters


• programmable full-duplex serial port
  (baud rate provided by one of the timers)


• 32 I/O lines (four 8-bit ports)


• RAM


• ROM/EPROM in some models
  

One strong point of the 8051 is the way it handles interrupts.
Vectoring to fixed 8-byte areas is convenient and efficient. Most
interrupt routines are very short (or at least they should be), and
generally can fit into the 8-byte area. Of course if your interrupt
routine is longer, you can still jump to the appropriate routine from
within the 8 byte interrupt region.

The 8051 instruction set is optimized for the one-bit operations so
often desired in real-world, real-time control applications. The
boolean processor provides direct support for bit manipulation. This
leads to more efficient programs that need to deal with binary input
and output conditions inherent in digital-control problems. Bit
addressing can be used for test pin monitoring or program control
flags.

See full information from 8051 FAQ
- http://www.faqs.org/faqs/microcontroller-faq/8051/